1. Field of the Invention
The invention relates in general to a method of designing an active region pattern with a shift dummy pattern, and more particularly, to a method adding a shift dummy pattern into an diffusion region for the process of forming a shallow trench isolation. Therefore, a better planarization effect is obtained in the subsequent process of chemical mechanical polishing (CMP), and a circuit problem induced by various parasitic capacitors is resolved.
2. Description of the Related Art
As the design of an integrated circuit is more and more complex, the line width of fabrication process reduced narrower than 1 .mu.m causes a restriction the development of a trench isolation technique in a complementary metal-oxide-semiconductor (CMOS) is thus restricted. While performing chemical mechanical polishing for planarization, if a under layer has a pattern on which the distance between devices is over 10 .mu.m, a dishing recess is formed on the region without a device thereon after polishing. Thus, a global planarization is affected. This is called as a dishing effect. In FIG. 1A to FIG. 1D, a shallow trench isolation formed by a conventional technique of chemical mechanical polishing is shown.
In FIG. 1A, on a semiconductor substrate 10, for example, a silicon substrate, a pad oxide layer 11 and a dielectric layer 12, for example, a silicon nitride layer are formed in sequence. Using photolithography and etching, a device region 13 is formed on the substrate 10. Using a photo-resist layer (not shown) on the device region 13 as a mask, the substrate 10 is etched, for example, by anisotropic etching, to form several trenches with certain depths. In FIG. 1B, using chemical vapor deposition (CVD), an oxide layer 14 is formed over the substrate 10. The oxide layer 14 is polished by chemical mechanical polishing with the dielectric layer 12 as a stop layer, so that several trench isolations 15, 16 are formed as shown in FIG. 1C.
After the formation of trench isolations 15, 16, subsequent processes, for example, removing the pad oxide layer 11 and the dielectric layer, forming a gate oxide layer 17 and a poly-silicon layer 18, is performed as shown in FIG. 1D. As shown in the figure, the width of each trench isolation is not identical. For example, the region of trench isolation 16 is larger than the region of the trench isolation 15. The poly-silicon layer 18 is well planarized on the trench isolation 15. On the contrary, the poly-silicon layer 18 on the trench isolation 15 has a smooth recess. Thus, using chemical mechanical polishing, only a local planarization is achieved. The global planarization cannot be achieved.
To resolve the drawback mentioned above, conventionally, a dummy pattern is added to the active region pattern to improve the uniformity of chemical mechanical polishing. However, a parasitic capacitance is induced by doing so to affect the performance of devices. The metal line on different dummy pattern causes a time delay by different parasitic capacitance, and therefore, causes a circuit problem. In FIG. 2, a conventional method of designing an active region pattern with a dummy pattern is shown. Metal lines 20, 22 are formed on different locations of the dummy pattern 24, and the dummy pattern 24 comprises columns 24a to 24d. For example, the metal line 20 is formed on a column 24c of the dummy pattern, and the metal line 22 covers a part of the column 24a and a part of the column 24b of the dummy pattern 24. Between the metal line 22 and the dummy pattern 24, different parasitic capacitance is induced in practical application, so that a problem of different time order, for example, an RC delay is caused.